Not an ML topic, but still about hardware. Hardware security evaluation of MAX10 intel FPGA. Invasive and non-invasive attacks
Huawei released MindSpor, Tensorflow style AI computing framework, in August 2019.
Announced support of the following hardware platforms: Ascend 910, high performance AI processor for training, and Ascend 310, power efficient AI processor. Probably, it should also include support of Kirin990, Huawei SoC of mobile devices.
On the last week Huawei announced that Mindspor is open source now.
Announced support of the following hardware platforms: Ascend 910, high performance AI processor for training, and Ascend 310, power efficient AI processor. Probably, it should also include support of Kirin990, Huawei SoC of mobile devices.
On the last week Huawei announced that Mindspor is open source now.
huawei
Huawei launches Ascend 910, the world's most powerful AI processor, and MindSpore, an all-scenario AI computing framework
Huawei officially launched the world's most powerful AI processor – the Ascend 910 – as well as an all-scenario AI computing framework, MindSpore.
Eetimes podcast
KEVIN KREWELL: Well, to my mind, once again, the Linley Conference (April 6-9) got taken over by AI companies. And in this case, I think the primary highlights were the AI companies. We got to see a new company, Tens Turnt (?), come to light and talk about their solution. Grok finally really opened up the kimono and talked about the internal architecture of their chip. And they were a show, not a no-show this time. The small guys were making progress. The very low power guys like Gray Matter, they’re all moving forward with their products. And I think were a number of IP companies. Actually, interesting, Flex Logic, which has been an IP company for FPGAs, sort of pivoted a bit. So they’re still making their FPGA stuff, but they’re also building dedicated chips for AI using a DSP core they created that works well for machine learning applications. So they actually went ahead and built their own chip, and they’re showing some great promise in terms of performance.
It was a lot of interesting technologies. A lot of the IP guys like Seefa had some really good DSP. ARM talked a little more about their accelerator for MCUs for Ethos U55, which is their machine learning accelerator. Not new, but it’s a key product dealing with ARM, which is a key vendor.
And then something completely different now was the RISC-V guys talking about vector processing (?). That’s the next wave of architecture changes for the RISC-V guys. They’re getting into vector processing and tightly coupling it to the instruction set of RISC-V CPUs.
KEVIN KREWELL: Well, to my mind, once again, the Linley Conference (April 6-9) got taken over by AI companies. And in this case, I think the primary highlights were the AI companies. We got to see a new company, Tens Turnt (?), come to light and talk about their solution. Grok finally really opened up the kimono and talked about the internal architecture of their chip. And they were a show, not a no-show this time. The small guys were making progress. The very low power guys like Gray Matter, they’re all moving forward with their products. And I think were a number of IP companies. Actually, interesting, Flex Logic, which has been an IP company for FPGAs, sort of pivoted a bit. So they’re still making their FPGA stuff, but they’re also building dedicated chips for AI using a DSP core they created that works well for machine learning applications. So they actually went ahead and built their own chip, and they’re showing some great promise in terms of performance.
It was a lot of interesting technologies. A lot of the IP guys like Seefa had some really good DSP. ARM talked a little more about their accelerator for MCUs for Ethos U55, which is their machine learning accelerator. Not new, but it’s a key product dealing with ARM, which is a key vendor.
And then something completely different now was the RISC-V guys talking about vector processing (?). That’s the next wave of architecture changes for the RISC-V guys. They’re getting into vector processing and tightly coupling it to the instruction set of RISC-V CPUs.
EETimes
AI Chip Revelations | A Corporate Soap Opera | The Sounds of a Pandemic - EETimes
Several secretive AI startups finally revealed what they’re doing – a conversation with analyst Kevin Krewell about the revelations from the Spring Linley Conference. Imagination Technologies got itself embroiled in international intrigue – what’s going on…
https://youtu.be/oxOvziuHHN0
The challenges of AI at the edge cannot merely be overcome by advances in AI software infrastructures. The solution lies in the critical rethinking of AI hardware at the edge, to achieve real-time processing with limited memory and the preservation of data privacy while not sacrificing the accuracy of the AI algorithms. Gain expert insights on this subject as Dr Sakya Dasgupta of Edgecortix Inc. shares his knowledge about edge computing and the challenges for enabling the future of AI at the edge. Date: 22 April 2020
Breaking Down Artificial Intelligence at the Edge by Dr Sakyasingha Dasgupta, Founder and CEO, Edgecortix, Inc.
The challenges of AI at the edge cannot merely be overcome by advances in AI software infrastructures. The solution lies in the critical rethinking of AI hardware at the edge, to achieve real-time processing with limited memory and the preservation of data privacy while not sacrificing the accuracy of the AI algorithms. Gain expert insights on this subject as Dr Sakya Dasgupta of Edgecortix Inc. shares his knowledge about edge computing and the challenges for enabling the future of AI at the edge. Date: 22 April 2020
Breaking Down Artificial Intelligence at the Edge by Dr Sakyasingha Dasgupta, Founder and CEO, Edgecortix, Inc.
Nanosemi (industry famous for PA linearization technology) announced availability of its NaNoTransformer technology. The technology operates at a mathematical level to augment mathematics of neural networks and generates implementations that provide higher accuracy or lower MACs. The output neural network can be targeted towards any platform such as CPU, GPU, FPGA or ASIC.
Wikipedia
Predistortion
Predistortion is a technique used to improve the linearity of radio transmitter amplifiers.
FCCM 2020
THE FUTURE OF FPGA-ACCELERATION IN
CLOUD AND DATA CENTERS
May 6th, 2020,
09:00 am - 03:00 pm PDT
Program
Zoom Event
THE FUTURE OF FPGA-ACCELERATION IN
CLOUD AND DATA CENTERS
May 6th, 2020,
09:00 am - 03:00 pm PDT
Program
Zoom Event
Telegram group of VLSI chaps @vlsi_chaps - ASIC chip developers community
We will share updates, news, Jobs, quizzes, codes, topics, Conferences, papers, PDFs, books, class notes, materials, discussion, query solving, research trends, tool suggestions, tool helps, tool reviews or any other help in the field of VLSI.
VLSI Chaps
https://www.tg-me.com/vlsi_chaps
We will share updates, news, Jobs, quizzes, codes, topics, Conferences, papers, PDFs, books, class notes, materials, discussion, query solving, research trends, tool suggestions, tool helps, tool reviews or any other help in the field of VLSI.
VLSI Chaps
https://www.tg-me.com/vlsi_chaps
Book publisher Springer just released over 400 book titles that can be downloaded free of charge following the corona-virus outbreak.
Here’s fhe full overview
Among them 65 ML and DS books, read the list of selected books here
Here’s fhe full overview
Among them 65 ML and DS books, read the list of selected books here
Medium
Springer has released 65 Machine Learning and Data books for free
Hundreds of books are now free to download
DRILLING DOWN INTO THE SIPEARL EUROPEAN ARM SERVER CHIP
The EU develops it's own server processor, both for general purposes and exascale computing. Matrix math and FPGA accelerators also coming from European suppliers.
Initiative is driving now by SiPearl, France bases start-up, just rai
Philippe Notton, CEO and founder, tells The Next Platform, the number of engineers working on the SiPearl Arm server chips – Rhea is the first generation and Chronos is the second generation – will grow to around 200 over the next two years as Rhea is created, tested, and ramped.
As to why Arm and not another core? For RISC-V, it is too early, and definitely so for a general purpose processor. X86 is not officially licensable and it is a bit too US-centric for what we are doing. And for us, Arm is much more neutral and what they are doing for HPC makes a lot of sense.”
The Rhea chip will support both DDR4 and DDR5 main memory as well as HBM main memory, PCI-Express 5.0 peripheral controllers and will support the CCIX protocol for hoking up accelerators over PCI-Express.
More about EPI
https://www.european-processor-initiative.eu/general-purpose-processor/
The EU develops it's own server processor, both for general purposes and exascale computing. Matrix math and FPGA accelerators also coming from European suppliers.
Initiative is driving now by SiPearl, France bases start-up, just rai
Philippe Notton, CEO and founder, tells The Next Platform, the number of engineers working on the SiPearl Arm server chips – Rhea is the first generation and Chronos is the second generation – will grow to around 200 over the next two years as Rhea is created, tested, and ramped.
As to why Arm and not another core? For RISC-V, it is too early, and definitely so for a general purpose processor. X86 is not officially licensable and it is a bit too US-centric for what we are doing. And for us, Arm is much more neutral and what they are doing for HPC makes a lot of sense.”
The Rhea chip will support both DDR4 and DDR5 main memory as well as HBM main memory, PCI-Express 5.0 peripheral controllers and will support the CCIX protocol for hoking up accelerators over PCI-Express.
More about EPI
https://www.european-processor-initiative.eu/general-purpose-processor/
The Next Platform
Drilling Down Into The SiPearl European Arm Server Chip
The European Union has made it clear that it wants to be able to stand on its own two feet in the design of server processors, for both general purpose
RISC-V V-extension (Vectorized or SIMD instructions extension) exploration by EPI
European Processor Initiative
V for vector: software exploration of the vector extension of RISC-V - European Processor Initiative
Introduction The European Processor Initiative (EPI) is building a new central processing unit (CPU) with European technology. This CPU will bundle an accelerator, based on the open source RISC-V architecture. This accelerator will include support for the…
For Russian speaking only, sorry for inconvenience
Russian telecom company Metrotek announced session of online webinars "Introduction to FPGA development".
This course is for beginners and free of charge. The very first lecture starts at 11th of May. See details below:
https://habr.com/ru/post/500770
Take a part if you wish don't look stupid with question "How can I launch my cpp code on FPGA" :)
PS: It's not a commercial promo, if you wish to share similar trainings in English, we will do it with pleasure.
Russian telecom company Metrotek announced session of online webinars "Introduction to FPGA development".
This course is for beginners and free of charge. The very first lecture starts at 11th of May. See details below:
https://habr.com/ru/post/500770
Take a part if you wish don't look stupid with question "How can I launch my cpp code on FPGA" :)
PS: It's not a commercial promo, if you wish to share similar trainings in English, we will do it with pleasure.
Хабр
Приглашаем на вебинар про FPGA для начинающих
Приветствую! Хочу сообщить, что скоро мы начинаем бесплатный online курс по FPGA! Первая лекция курса пройдёт 11 мая, начало в 18:00 на канале Twitch MaksimTolkachev. Всю информацию о курсе Вы можете...